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hyb25d128160c[e/t] hyb25d128400c[c/e/t] hyb25d128800c[c/e/f/t] 128-mbit double-data-rate sdram ddr sdram internet data sheet rev. 1.70 april 2008
internet data sheet hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram qag_techdoc_a4, 4.20, 2008-01-25 2 03292006-u5an-6ti1 we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com revision history: rev. 1.70, 2008-04 adapted internet edition added more products previous revision: rev. 1.62, 2007-11 editorial change previous revision: rev. 1.61, 2007-10 editorial change previous revision: rev. 1.60, 2006-02 added hyb25d128800ce-7 and hyb25d128800ct-5
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 3 03292006-u5an-6ti1 1overview this chapter gives an overview of the 128-mbit doub le-data-rate sdram product family and describes its main characteristics. 1.1 features ? double data rate architecture: tw o data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? programmable burst lengths: 2, 4, or 8 ? programmable drive strength: normal, weak ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ? 15.6 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v dd = 2.5 v 0.2 v (ddr266, ddr333), v dd = 2.6 v 0.1 v (ddr400) ? v ddq = 2.5 v 0.2 v (ddr266, ddr333), v ddq = 2.6 v 0.1 v (ddr400) ? packages: p-tsopii-66, pg-tsopii-66, p-tfbga-60 table 1 performance part number speed code ?5 ?6 ?7 unit speed grade ddr400b ddr333b ddr266a ? max. clock frequency @cl3 f ck3 200 166 ? mhz @cl2.5 f ck2.5 166 166 143 mhz @cl2 f ck2 133 133 133 mhz
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 4 03292006-u5an-6ti1 1.2 description the 128-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 134, 217, 728 bits. it is internally configured as a quad-bank dram. the 128-mbit double-data-rate sdram uses a double- data-rate architecture to ac hieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128-mbit double-data-rate sdram effectively consists of a singl e 2n-bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-ha lf-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (d qs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller dur ing writes. dqs is edge-aligned with data for reads and center-a ligned with data for writes. the 128-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipel ined, multibank architecture of ddr sdrams allows for co ncurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the industry standard for sstl_2. all out puts are sstl_2, class ii compatible. note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation.
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 5 03292006-u5an-6ti1 table 2 ordering information for rohs compliant products table 3 ordering information for lead-containing products product type 1) 1) for detailed information regarding product type of qimonda pl ease see chapter "product nomenc lature" of this data sheet. org. speed cas-rcd-rp latencies 2)3)4) 2) cas: column address strobe 3) rcd: row column delay 4) rp: row precharge clock (mhz) package note 5) 5) rohs compliant product: restriction of the use of certain hazardous substances (r ohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, pol ybrominated biphenyls and polybro minated biphenyl ethers. for more information please vi sit www.qimonda.com/green_products . standard temperature range (0 c - 70 c) ddr400b( 3-3-3 ) hyb25d128160ce-5 16 ddr400b 3-3-3 200 pg-tsopii-66 hyb25d128800ce-5 8 ddr400b 3-3-3 200 pg-tsopii-66 hyb25d128160cf-5 16 ddr400b 3-3-3 200 p-tfbga-60 hyb25d128400ce-5 4 ddr400b 3-3-3 200 p-tsopii-66 hyb25d128800cf-5 8 ddr400b 3-3-3 200 p-tfbga-60 ddr333b( 2.5-3-3 ) hyb25d128160ce-6 16 ddr333b 2.5-3-3 166 pg-tsopii-66 hyb25d128400ce-6 4 ddr333b 2.5-3-3 166 pg-tsopii-66 hyb25d128800ce-6 8 ddr333b 2.5-3-3 166 pg-tsopii-66 HYB25D128160CF-6 16 ddr333b 2.5-3-3 166 p-tfbga-60 hyb25d128800cf-6 8 ddr333b 2.5-3-3 166 p-tfbga-60 ddr266a( 2-3-3 ) hyb25d128400ce-7 4 ddr266a 2-3-3 133 p-tsopii-66 hyb25d128800ce-7 8 ddr266a 2-3-3 133 pg-tsopii-66 product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note standard temperature range (0 c - 70 c) ddr400b( 3-3-3 ) hyb25d128160ct-5 16 ddr400b 3-3-3 200 p-tsopii-66 hyb25d128400cc-5 4 ddr400b 3-3-3 200 p-tfbga-60 hyb25d128400ct-5 4 ddr400b 3-3-3 200 p-tsopii-66 hyb25d128800cc-5 8 ddr400b 3-3-3 200 p-tfbga-60 hyb25d128800ct-5 8 ddr400b 3-3-3 200 p-tsopii-66 ddr333b( 2.5-3-3 ) hyb25d128160ct-6 16 ddr333b 2.5-3-3 166 p-tsopii-66
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 6 03292006-u5an-6ti1 hyb25d128400cc-6 4 ddr333b 2.5-3-3 166 p-tfbga-60 hyb25d128400ct-6 4 ddr333b 2.5-3-3 166 p-tsopii-66 hyb25d128800cc-6 8 ddr333b 2.5-3-3 166 p-tfbga-60 hyb25d128800ct-6 8 ddr333b 2.5-3-3 166 p-tsopii-66 ddr266a( 2-3-3 ) hyb25d128400ct-7 4 ddr266a 2-3-3 133 p-tsopii-66 1) for detailed information regarding product type of qimonda pl ease see chapter "product nomenc lature" of this data sheet. 2) cas: column address strobe 3) rcd: row column delay 4) rp: row precharge product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 7 03292006-u5an-6ti1 2 configuration this chapter contains the chip configuration and block diagrams. 2.1 configuration for tfbga-60 the ball configuration of a ddr s dram is listed by function in table 4 . the abbreviations used in the ball#/buffer type column are explained in table 5 and table 6 respectively. table 4 configuration ball# name pin type buffer type function clock signals g2 ck1 i sstl clock signal g3 ck1 i sstl complementary clock signal h3 cke i sstl clock enable control signals h7 ras i sstl row address strobe g8 cas i sstl column address strobe g7 we i sstl write enable h8 cs i sstl chip select address signals j8 ba0 i sstl bank address bus j7 ba1 i sstl k7 a0 i sstl address bus l8 a1 i sstl l7 a2 i sstl m8 a3 i sstl m2 a4 i sstl l3 a5 i sstl l2 a6 i sstl k3 a7 i sstl k2 a8 i sstl j3 a9 i sstl k8 a10 i sstl ap i sstl j2 a11 i sstl
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 8 03292006-u5an-6ti1 data signals 4 organization b7 dq0 i/o sstl data signal bus 3:0 d7 dq1 i/o sstl d3 dq2 i/o sstl b3 dq3 i/o sstl data strobe 4 organization e3 dqs i/o sstl data strobe data mask 4 organization f3 dm i sstl data mask data signals 8 organization a8 dq0 i/o sstl data signal bus 7:0 b7 dq1 i/o sstl c7 dq2 i/o sstl d7 dq3 i/o sstl d3 dq4 i/o sstl c3 dq5 i/o sstl b3 dq6 i/o sstl a2 dq7 i/o sstl data strobe 8 organization e3 dqs i/o sstl data strobe data mask 8 organization f3 dm i sstl data mask data signals 16 organization a8 dq0 i/o sstl data signal 15:0 b9 dq1 i/o sstl b7 dq2 i/o sstl c9 dq3 i/o sstl c7 dq4 i/o sstl d9 dq5 i/o sstl d7 dq6 i/o sstl e9 dq7 i/o sstl e1 dq8 i/o sstl d3 dq9 i/o sstl d1 dq10 i/o sstl c3 dq11 i/o sstl c1 dq12 i/o sstl b3 dq13 i/o sstl b1 dq14 i/o sstl a2 dq15 i/o sstl ball# name pin type buffer type function
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 9 03292006-u5an-6ti1 table 5 abbreviations for ball type data strobe 16 organization e3 udqs i/o sstl data strobe upper byte e7 ldqs i/o sstl data strobe lower byte data mask 16 organization f3 udm i sstl data mask upper byte f7 ldm i sstl data mask lower byte power supplies f1 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8 v ddq pwr ? i/o driver power supply a7, f8, m7 v dd pwr ? power supply a1, b8, c2, d8, e2 v ssq pwr ? power supply a3, f2, m3 v ss pwr ? power supply not connected 4 organization a2, a8, b1, b9, c1, c3, c7, c9, d1, d9, e1, e7, e9, f7, f9 nc nc ? not connected not connected 8 organization b1, b9, c1, c9, d1, d9, e1, e7, e9, f7, f9, h2 nc nc ? not connected not connected 16 organization f9, h2 nc nc ? not connected abbreviation description i standard input-only pin. digital levels o output. digital levels i/o i/o is a bidirectional input/output signal ai input. analog levels pwr power gnd ground nc not connected ball# name pin type buffer type function
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 10 03292006-u5an-6ti1 table 6 abbreviations for buffer type figure 1 configuration for x4 orga nization, tfbga-60, top view abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or &$6 &6 033' 9 664 '46 &. 1& 1& 1& 1& 9 5() 1& 9 ''4 9 664 9 ''4 9 664 9 66 1& $ $ $ $ &. &.( $ $ $ 9 66 '0 '4 1& '4 9 66 :( 5$6 %$ $ $ 9 '' '4 1& '4 9 '' 1& 1& 1& 9 664 9 ''4 9 664 9 '' %$ $$3 $ $ 9 ''4 9 ''4 1& 1& 1& 1& 1& $ % & ' ) * + - ( / 0 . [
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 11 03292006-u5an-6ti1 figure 2 configuration for x8 orga nization, tfbga-60, top view 033' &$6 &6 9 664 '46 &. 1& 1& 1& 1& 9 5() '4 9 ''4 9 664 9 ''4 9 664 9 66 1& $ $ $ $ &. &.( $ $ $ 9 66 '0 '4 '4 '4 9 66 :( 5$6 %$ $ $ 9 '' '4 '4 '4 9 '' 1& 1& '4 9 664 9 ''4 9 664 9 '' %$ $$3 $ $ 9 ''4 9 ''4 1& 1& 1& 1& 1& $ % & ' ) * + - ( / 0 . [
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 12 03292006-u5an-6ti1 figure 3 configuration for x16 orga nization, tfbga-60, top view 033' 8'46 &. '4 '4 '4 '4 9 5() '4 9 ''4 9 664 9 ''4 9 664 9 66 1& $ $ $ $ &.( $ $ $ 9 66 8'0 '4 '4 '4 9 66 $ % & ' ) * + - ( / 0 . [ &. %$ $ $ 9 '' '4 '4 '4 9 '' /'46 /'0 '4 9 664 9 ''4 9 664 9 '' %$ $$3 $ $ 9 ''4 9 ''4 '4 '4 '4 '4 1& :( &$6 5$6 &6 9 664
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 13 03292006-u5an-6ti1 2.2 configuration for tsopii-66 the pin configuration of a ddr sdram is listed by function in table 7 . the abbreviations used in the pin#/buffer type column are explained in table 8 and table 9 respectively. table 7 configuration pin# name pin type buffer type function clock signals 45 ck i sstl clock signal 46 ck i sstl complementary clock signal 44 cke i sstl clock enable control signals 23 ras i sstl row address strobe 22 cas i sstl column address strobe 21 we i sstl write enable 24 cs i sstl chip select address signals 26 ba0 i sstl bank address bus 27 ba1 i sstl 29 a0 i sstl address bus 30 a1 i sstl 31 a2 i sstl 32 a3 i sstl 35 a4 i sstl 36 a5 i sstl 37 a6 i sstl 38 a7 i sstl 39 a8 i sstl 40 a9 i sstl 28 a10 i sstl ap i sstl 41 a11 i sstl data signals 4 organization 5 dq0 i/o sstl data signal bus 3:0 11 dq1 i/o sstl 56 dq2 i/o sstl 62 dq3 i/o sstl data strobe 4 organization 51 dqs i/o sstl data strobe
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 14 03292006-u5an-6ti1 data mask 4 organization 47 dm i sstl data mask data signals 8 organization 2 dq0 i/o sstl data signal bus 7:0 5 dq1 i/o sstl 8 dq2 i/o sstl 11 dq3 i/o sstl 56 dq4 i/o sstl 59 dq5 i/o sstl 62 dq6 i/o sstl 65 dq7 i/o sstl data strobe 8 organization 51 dqs i/o sstl data strobe data mask 8 organization 47 dm i sstl data mask data signals 16 organization 2 dq0 i/o sstl data signal 15:0 4 dq1 i/o sstl 5 dq2 i/o sstl 7 dq3 i/o sstl 8 dq4 i/o sstl 10 dq5 i/o sstl 11 dq6 i/o sstl 13 dq7 i/o sstl 54 dq8 i/o sstl 56 dq9 i/o sstl 57 dq10 i/o sstl 59 dq11 i/o sstl 60 dq12 i/o sstl 62 dq13 i/o sstl 63 dq14 i/o sstl 65 dq15 i/o sstl data strobe 16 organization 51 udqs i/o sstl data strobe upper byte 16 ldqs i/o sstl data strobe lower byte data mask 16 organization 47 udm i sstl data mask upper byte 20 ldm i sstl data mask lower byte power supplies 49 v ref ai ? i/o reference voltage pin# name pin type buffer type function
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 15 03292006-u5an-6ti1 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply 1, 18, 33 v dd pwr ? power supply 6, 12, 52, 58, 64 v ssq pwr ? power supply 34,48, 66 v ss pwr ? power supply not connected 4 organization 2, 4, 7, 8, 10, 13, 14, 16, 17, 19, 20, 25, 42, 43, 50, 53, 54, 57, 59, 60, 63, 65 nc nc ? not connected not connected 8 organization 4, 7, 10, 13, 14, 16, 17, 19, 20, 25, 42, 43, 50, 53, 54, 57, 60, 63 nc nc ? not connected not connected 16 organization 14, 17, 19, 25, 42, 43, 50, 53 nc nc ? not connected pin# name pin type buffer type function
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 16 03292006-u5an-6ti1 table 8 abbreviations for pin type table 9 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels o output. digital levels i/o i/o is a bidirectional input/output signal ai input. analog levels pwr power gnd ground nc not connected abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 17 03292006-u5an-6ti1 figure 4 pin configuration tsopii-66 033' 9 '' '4 9 ''4 9 664 '4 '4 9 ''4 '4 '4 '4 '4 9 664 '4 9 ''4 1& /'46 1& 9 '' 1& /'0 :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 '' '4 9 ''4 9 664 1& '4 9 ''4 1& '4 1& '4 9 664 1& 9 ''4 1& 1& 1& 9 '' 1& 1& :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 '' 1& 9 ''4 9 664 1& '4 9 ''4 1& 1& 1& '4 9 664 1& 9 ''4 1& 1& 1& 9 '' 1& 1& :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 66 '4 9 664 9 ''4 '4 '4 9 664 '4 '4 '4 '4 9 ''4 '4 9 664 1& 8'46 1& 9 5() 8'0 &. &. &.( 1& 1& $ $ $ $ $ $ $ 9 66 9 66 9 66 '4 9 664 9 ''4 1& '4 9 664 1& '4 1& '4 9 ''4 1& 9 664 1& '46 1& 9 5() '0 &. &. &.( 1& 1& $ $ $ $ $ $ $ 9 66 9 66 9 66 1& 9 664 9 ''4 1& '4 9 664 1& 1& 1& '4 9 ''4 1& 9 664 1& '46 1& 9 5() '0 &. &. &.( 1& 1& $ $ $ $ $ $ $ 9 66 9 66 [ [ [
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 18 03292006-u5an-6ti1 3 functional description the 128-mbit double-data-rate sdram uses a double-da ta-rate architecture to achieve high-speed operation. 3.1 mode register definition the mode register is used to define the sp ecific mode of operation of the ddr sdram. table 10 mode register definition field bits type 1) 1) w = write only register bit description bl [2:0] w burst length note: all other bit combinations are reserved. 001 b 2 010 b 4 011 b 8 bt 3 burst type 0 sequential 1 interleaved cl [6:4] cas latency note: all other bit combinations are reserved. 010 b 2 110 b 2.5 011 b 3 mode [11:7] operating mode note: all other bit combinations are reserved. 00000 normal operation without dll reset 00010 normal operation with dll reset 03%' %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ 02'( %/ &/ %7 uhjdggu zzzz
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 19 03292006-u5an-6ti1 3.1.1 burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 11 . table 11 burst definition notes 1. for a burst length of two, a1-ai selects the two-data-el ement block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai sele cts the four-data-elem ent block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block. burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 200-10-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 20 03292006-u5an-6ti1 3.2 extended mode register the extended mode register contro ls functions beyond those controlled by the mode register. table 12 extended mode register field bits type 1) 1) w = write only register bit description dll 0w dll status 0 b enabled 1 b disabled ds 1 drive strength 0 b normal 1 b weak mode [11:2] operating mode 0000000000 b normal operation notes. 1. a2 must be 0 to provide compatibility with early ddr devices. 2. all other bit combinations are reserved. 03%' %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ 02'( '6 '//
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 21 03292006-u5an-6ti1 4 truth tables the truth tables in this chapter summa rize the commands and there signal coding to control a standard double-data-rate sdram. table 13 truth table 1: commands 1) cke is high for all commands shown exceptself refresh. v ref must be maintained during self refresh operation. 2) deselect and nop are functionally interchangeable. 3) ba0, ba1 provide bank address and a0 - ai provide row address. 4) ba0, ba1 provide bank address; a0 - ai pr ovide column address; a10 high enables t he auto precharge feature (nonpersistent), a 10 low disables the auto precharge feature. 5) applies only to read bursts with auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts. 6) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. 7) this command is auto refresh if cke is high; self refresh if cke is low 8) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. 9) ba0, ba1 select either the base or the extended mode register ( ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0 - ai provide the op-code to be written to the selected m ode register. table 14 truth table 2: dm operation name (function) cs ras cas we address mne note deselect (nop) h x x x x nop 1)2) no operation (nop) l h h h x nop 1)2) active (select bank and activate row) l l h h bank/row act 1)3) read (select bank and column, and start read burst) l h l h bank/col read 1)4) write (select bank and column, and start write burst) l h l l bank/col write 1)4) burst terminate l h h l x bst 1)5) precharge (deactivate row in bank or banks) l l h l code pre 1)6) auto refresh or self refresh (e nter self refresh mode) l l l h x ar/sr 1)7)8) mode register set l l l l op-code mrs 1)9) name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit hx
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 22 03292006-u5an-6ti1 table 15 truth table 3: clock enable (cke) 1. cken is the logic state of cke at clock edge n: ck e n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x maintain self-refresh 1) 1) v ref must be maintained during self refresh operation self refresh l h deselect or nop exit self-refresh 2) 2) deselect or nop commands should be issued on any cl ock edges occurring during the self refresh exit ( t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock. power down l l x maintain power-down ? power down l h deselect or nop exit power-down ? all banks idle h l deselect or nop precharge power-down entry ? all banks idle h l auto refresh self refresh entry ? bank(s) active h l deselect or nop active power-down entry ? h h see table 16 ??
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 23 03292006-u5an-6ti1 table 16 truth table 4: current state bank n - command to bank n (same bank) 1) this table applies when cke n-1 was high and cke n is high (see table 15 and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table is bank-specific, ex cept where noted, i.e., the current state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminat ed. write: a write burst has been initiated, with auto prec harge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row ac tivating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? stat e. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registra tion of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or no p commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable co mmands to the other bank are determined by its current stat e and according to table 17 . 5) the following states must not be interrupted by any execut able command; deselect or nop commands must be applied on each posi tive clock edge during these states. refreshi ng: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing m ode register: starts with registration of a mode register set c ommand and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle. 8) reads or writes listed in the command/action column include read s or writes with auto precharge enabled and reads or writes w ith auto precharge disabled. 9) may or may not be bank-specific; if al l/any banks are to be precharged, all/any must be in a valid state for precharging. 10) not bank-specific; burst terminate affects th e most recent read burst, regardless of bank. 11) requires appropriate dm masking. current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation. 1)2)3)4)5)6) l h h h no operation nop. continue previous operation. 1)2)3)4)5)6) idle l l h h active select and activate row 1)2)3)4)5)6) ll lhauto refresh ? 1)2)3)4)5)6)7) l l l l mode register set ? 1)2)3)4)5)6)7) row active l h l h read select column and start read burst 1)2)3)4)5)6)8) l h l l write select column and start write burst 1)2)3)4)5)6)8) l l h l precharge deactivate row in bank(s) 1)2)3)4)5)6)9) read (auto precharge disabled) l h l h read select column and start new read burst 1)2)3)4)5)6)8) l l h l precharge truncate read burst, start precharge 1)2)3)4)5)6)9) l h h l burst terminate burst terminate 1)2)3)4)5)6)10) write (auto precharge disabled) l h l h read select column and start read burst 1)2)3)4)5)6)8)11) l h l l write select column and start write burst 1)2)3)4)5)6)8) l l h l precharge truncate write burst, start precharge 1)2)3)4)5)6)9)11)
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 24 03292006-u5an-6ti1 table 17 truth table 5: current state bank n - command to bank m (different bank) 1) this table applies when cke n-1 was high and cke n is high (see table 15 : clock enable (cke) and after t xsnr / t xsrd has been met, if the previous state was self refresh) 2) this table describes alternate bank opera tion, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are co vered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminat ed. write: a write burst has been initiated, with auto prec harge disabled, and has not yet terminated or been terminated. 4) auto refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved. 7) reads or writes listed in the command/action column include read s or writes with auto precharge enabled and reads or writes w ith auto precharge disabled. 8) requires appropriate dm masking. 9) concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as l ong as that command does not interrupt the read or write dat a current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation 1)2)3)4)5)6) l h h h no operation nop. continue previous operation 1)2)3)4)5)6) idle x x x x any command otherwise allowed to bank m ? 1)2)3)4)5)6) row activating, active, or precharging l l h h active select and activate row 1)2)3)4)5)6) l h l h read select column and start read burst 1)2)3)4)5)6)7) l h l l write select column and start write burst 1)2)3)4)5)6)7) l l h l precharge ? 1)2)3)4)5)6) read (auto precharge disabled) l l h h active select and activate row 1)2)3)4)5)6) l h l h read select column and start new read burst 1)2)3)4)5)6)7) l l h l precharge ? 1)2)3)4)5)6) write (auto precharge disabled) l l h h active select and activate row 1)2)3)4)5)6) l h l h read select column and start read burst 1)2)3)4)5)6)7)8) l h l l write select column and start new write burst 1)2)3)4)5)6)7) l l h l precharge ? 1)2)3)4)5)6) read (with auto precharge) l l h h active select and activate row 1)2)3)4)5)6) l h l h read select column and start new read burst 1)2)3)4)5)6)7)9) l h l l write select column and start write burst 1)2)3)4)5)6)7)9)10) l l h l precharge ? 1)2)3)4)5)6) write (with auto precharge) l l h h active select and activate row 1)2)3)4)5)6) l h l h read select column and start read burst 1)2)3)4)5)6)7)9) l h l l write select column and start new write burst 1)2)3)4)5)6)7)9) l l h l precharge ? 1)2)3)4)5)6)
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 25 03292006-u5an-6ti1 transfer and all other limitations apply (e .g. contention between read data and write data must be avoided). the minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 18 . 10) a write command may be applied after the completion of data output. table 18 truth table 6: concurrent auto precharge from command to command (different bank) minimum delay with concurrent auto precharge support unit write w/ap read or read w/ap 1 + (bl/2) + t wtr t ck write to write w/ap bl/2 t ck precharge or activate 1 t ck read w/ap read or read w/ap bl/2 t ck write or write w/ap cl (rounded up) + bl/2 t ck precharge or activate 1 t ck
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 26 03292006-u5an-6ti1 5 electrical characteristics this chapter describes the electrical characteristics. 5.1 operating conditions this chapter contains the operating conditions tables. table 19 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. parameter symbol values unit note min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c storage temperature (plastic) t stg ?55 ? +150 c? power dissipation (per sdram component) p d ?1? w? short circuit output current i out ?50? ma?
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 27 03292006-u5an-6ti1 table 20 input and output capacitances parameter symbol values unit note/ test condition min. typ. max. input capacitance: ck, ck c i1 2.0 ? 3.0 pf tsopii 1) 1) these values are guaranteed by design and are tested on a sample base only. v ddq = v dd = 2.5 v 0.2 v, f = 100 mhz, t a = 25 c, v out(dc) = v ddq /2, v out (peak to peak) 0.2 v. unused pins are tied to ground. 1.5 ? 2.5 pf tfbga 1) delta input capacitance c di1 ? ? 0.25 pf 1) input capacitance: all other input-only pins c i2 1.5 ? 2.5 pf tfbga 1) 2.0 ? 3.0 pf tsopii 1) delta input capacitance: all other input-only pins c dio ?? 0.5pf 1) input/output capacitance: dq, dqs, dm c io 3.5 ? 4.5 pf tfbga 1)2) 2) dm inputs are grouped with i/o pins reflec ting the fact that they are matched in l oading to dq and dqs to facilitate trace ma tching at the board level. 4.0 ? 5.0 pf tsopii 1)2) delta input/output capaci tance: dq, dqs, dm c dio ?? 0.5pf 1)
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 28 03292006-u5an-6ti1 table 21 electrical characteristics and dc operating conditions 1) 0 c t a 70 c; v dd = v ddq = 2.5 v 0.2 v 2) under all conditions, v ddq must be less than or equal to v dd . 3) peak to peak ac noise on v ref may not exceed 2% v ref.dc . v ref is also expected to tr ack noise variations in v ddq . 4) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 5) inputs are not recognized as valid until v ref stabilizes. 6) v id is the magnitude of the difference between the input level on ck and the input level on ck . 7) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. 8) values are shown per pin. parameter symbol values un it note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 200 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 200 mhz 2) supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 3) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 4) input high (logic1) voltage v ih.dc v ref + 0.15 v ddq + 0.3 v 5) input low (logic0) voltage v il.dc ?0.3 v ref ? 0.15 v 5) input voltage level, ck and ck inputs v in.dc ?0.3 v ddq + 0.3 v 5) input differential voltage, ck and ck inputs v id.dc 0.36 v ddq + 0.6 v 5)6) vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7) input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 8) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol ?16.2 ? ma v out = 0.35 v
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 29 03292006-u5an-6ti1 5.2 ac characteristics notes 1-5 apply to the following tables; electrical characteri stics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and elec trical characteristics and ac timing. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal re ference/supply voltage levels, but the related specifications and device oper ation are guaranteed for the full voltage range specified. 3. figure 5 represents the timing reference load used in defining the re levant timing parameters of the part. it is not intended to be either a precise representation of the typical system environm ent nor a depiction of the ac tual load presented by a production tester. system designers will use ibis or other simula tion tools to correlate the ti ming reference load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5 v in the test environ ment, but input timing is still referenced to v ref (or to the crossi ng point for ck, ck ), and parameter spec ifications are guaranteed for t he specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e . the receiver effectively switches as a result of the signal crossing the ac input level, and remain s in that state as long as the signal does not ring back above (below) the dc input low (high) level). 6. for system characteristics like setup & holdtime derating for slew rate, i/o delta rise/ fall derating, ddr sdram slew rate standards, overshoot & undershoot specification and clamp v - i characteristics see the latest industry specification for ddr components. figure 5 ac output load circuit diagram / timing reference load
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 30 03292006-u5an-6ti1 table 22 ac operating conditions 1) 0 c t a 70 c; v dd = v ddq = 2.5 v 0.2 v 2) input slew rate = 1 v/ns. 3) inputs are not recognized as valid until v ref stabilizes. 4) v id is the magnitude of the difference between the input level on ck and the input level on ck . 5) the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must track variations in the dc level of the same. parameter symbol values unit note/ test condition min. max. input high (logic 1) voltage, dq, dqs and dm signals v ih.ac v ref + 0.31 ? v 1)2)3) input low (logic 0) voltage, dq, dqs and dm signals v il.ac ? v ref ? 0.31 v 1)2)3) input differential voltage, ck and ck inputs v id.ac 0.7 v ddq + 0.6 v 1)2)3)4) input closing point voltage, ck and ck inputs v ix.ac 0.5 v ddq ? 0.2 0.5 v ddq + 0.2 v 1)2)3)5)
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 31 03292006-u5an-6ti1 table 23 ac timing - absolute specifications parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333b min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal min. : ( t wr / t ck )+( t rp / t ck ), max. : ? t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.45 ns tsopii 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch ) ?min. ( t cl , t ch ) ?ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ? +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9)
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 32 03292006-u5an-6ti1 address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.55 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ? 15.6 ? 15.6 s 2)3)4)5)8) auto-refresh to active/auto- refresh command period t rfc 68 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre max. (0.25 t ck , 1.5 ns) ? max. (0.25 t ck , 1.5 ns) ?ns 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)10) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)11) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333b min. max. min. max.
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 33 03292006-u5an-6ti1 table 24 ac timing - absolute specifications parameter symbol ?7 unit note/ test condition 1) ddr266a min. max. dq output access time from ck/ck t ac ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 7.5 12 ns cl = 3.0 2)3)4)5) 7.5 12 ns cl = 2.5 2)3)4)5) 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.5 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.75 +0.75 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and a ssociated dq signals) t dqsq ? +0.5 ns tsopii 2)3)4)5) dqs-dq skew (dqs and a ssociated dq signals) t dqsq ?+0.5nstfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.5 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck 2)3)4)5) dqs falling edge to ck se tup time (write cycle) t dss 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? ns 2)3)4)5) dq & dqs high-impedance time from ck/ck t hz ? +0.75 ns 2)3)4)5)7) address and control input hold time t ih 0.9 ? ns fast slew rate 3)4)5)6)8) 1.0 1.1 ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.9 ? ns fast slew rate 3)4)5)6)8) 1.0 ? ns slow slew rate 3)4)5)6)8) dq & dqs low-impedance time from ck/ck t lz ?0.75 +0.75 ns 2)3)4)5)7) mode register set command cycle time t mrd 2? t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.75 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.75 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd or t rasmin ?ns 2)3)4)5) active to precharge command t ras 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 65 ? ns 2)3)4)5)
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 34 03292006-u5an-6ti1 1) 0 c t a 70 c; v dd = v ddq = 2.5 v 0.2 v (ddr266a, ddr333b); v dd = v ddq = +2.6 v 0.1 v (ddr400). 2) input slew rate 1 v/ns. 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih.ac and v il.ac . 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) the specific requirement is that dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specificationsof the device. w hen no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low at this time , depending on t dqss . 11) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. active to read or write delay t rcd 20 ? ns 2)3)4)5) average periodic refresh interval t refi ? 15.6 s 2)3)4)5)8) auto-refresh to active/auto-refresh command period t rfc 75 ? ns 2)3)4)5) precharge command period t rp 20 ? ns 2)3)4)5) read preamble t rpre 0.9 1.0 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 15 ? ns 2)3)4)5) write preamble t wpre 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?ns 2)3)4)5)10) write postamble t wpst 0.40 0.60 t ck 2)3)4)5)11) write recovery time t wr 15 ns 2)3)4)5) internal write to read command delay t wtr 1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? t ck 2)3)4)5) parameter symbol ?7 unit note/ test condition 1) ddr266a min. max.
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 35 03292006-u5an-6ti1 table 25 i dd conditions parameter symbol operating current: one bank; active/ precharge; t rc = t rcmin ; t ck = t ckmin ; dq, dm, and dqs inputs changing once per clock cycle ; address and control inputs changing once every two clock cycles. i dd0 operating current: one bank; active/read/precharge; burst = 4; refer to the following page for detailed test conditions. i dd1 precharge power-down standby current: all banks idle; power-down mode; cke v ilmax ; t ck = t ckmin i dd2p precharge floating standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs stable at v ihmin or v ilmax ; v in = v ref for dq, dqs and dm. i dd2q active power-down standby current: one bank active; power-down mode; cke v ilmax ; t ck = t ckmin ; v in = v ref for dq, dqs and dm. i dd3p active standby current: one bank active; cs v ihmin ; cke v ihmin ; t rc = t rasmax ; t ck = t ckmin ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle i dd3n operating current: one bank active; burst = 2; reads; continuo us burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin ; i out =0ma i dd4r operating current: one bank active; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin i dd4w auto-refresh current: t rc = t rfcmin , burst refresh i dd5 self-refresh current: cke 0.2 v; external clock on; t ck = t ckmin i dd6 operating current: four bank; four bank interleaving with bl = 4; refer to the following page for detailed test conditions. i dd7
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 36 03292006-u5an-6ti1 table 26 i dd specification 1) test conditions fo r typical values: v dd = 2.5 v (ddr266, ddr333), v dd = 2.6 v (ddr400), t a = 25 c, test conditions for maximum values: v dd = 2.7 v, t a = 10 c. 2) i dd specifications are tested after the de vice is properly initialized and measured at 133mhz for ddr266, 166 mhz for ddr333 and 20 0 mhz for ddr400. 3) input slew rate = 1 v/ns. 4) enables on-chip refresh and address counters. ?5 ?6 ?7 unit note/test condition 1) ddr400b ddr333 ddr266a symbol typ. max. typ. max. typ. max. i dd0 70 90 60 75 50 65 ma 4/ 8 2)3) 75 90 65 75 55 65 ma 16 i dd1 80 100 70 85 65 75 ma 4/ 8 95 110 80 95 70 85 ma 16 i dd2p 453.54.534ma i dd2f 30 36 25 30 20 24 ma i dd2q 20 28 17 24 15 21 ma i dd3p 13 18 11 15 9 13 ma i dd3n 38 45 32 38 28 36 ma 4/ 8 43 54 36 45 30 40 ma 16 i dd4r 85 100 70 85 60 70 ma 4/ 8 100 120 85 100 70 85 ma 16 i dd4w 90 105 75 90 65 75 ma 4/ 8 100 130 90 110 75 90 ma 16 i dd5 140 190 120 160 100 140 ma i dd6 1.4 2.8 1.4 2.8 1.4 2.8 ma standard version 4) i dd7 210 250 180 215 140 170 ma 4/ 8 210 250 180 215 140 170 ma 16
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 37 03292006-u5an-6ti1 6 package outlines the package used for this product family. notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 figure 6 package outline p(g)-tsopii-66 $ o e s n o t i n c l u d e p l a s t i c p r o t r u s i o n o f m a x p e r s i d e $ o e s n o t i n c l u d e d a m b a r p r o t r u s i o n o f m a x $ o e s n o t i n c l u d e p l a s t i c o r m e t a l p r o t r u s i o n o f m a x p e r s i d e ? ? ? ? ? ? ? x ? - x - ! 8 - ! 8 ) n d e x - a r k i n g ? ? ? ? ? ? ? ? ? ? x 3 % ! 4 ) . ' 0 , ! . % ? ? - ) . ' ! 5 ' % 0 , ! . % & 0 / ? 0 ? 4 3 / 0 ) ) ?
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 38 03292006-u5an-6ti1 figure 7 package outline p-tfbga-60 &0/?0? 4&"'!?? -iddle of packages edges "ad unit marking "5- ! marking chipside ! marking ballside $ummy pads without ball x -!8 x " ! -!8 -!8 -). # ? ? ? ? x - - ! # # " 3%!4).' 0,!.% # #
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 39 03292006-u5an-6ti1 figure 8 package outline p-tfbga-60 &0/?0' 4&"'!?? -iddle of packages edges "ad unit marking "5- ! marking chipside ! marking ballside $ummy pads without ball x -!8 x " ! -!8 -!8 -). # ? ? ? ? x - - ! # # " 3%!4).' 0,!.% # # ,ead free green solder balls
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 40 03292006-u5an-6ti1 7 product nomenclature for reference the qimonda sdram component nomenclature is enclosed in this chapter. table 27 example for nomenclature fields table 28 ddr memory components example for field number 12345678910 ddr sdram hyb 25 d 256 80 0 d e ?5 field description values coding 1 qimonda component prefix hyb memory components hyi memory components, industrial te mperature range (-40c ? +85 c) 2 interface voltage [v] 25 2.5 v 3 dram technology d double data rate sdram 4 component density [mbit] 64 64 mbit 128 128 mbit 256 256 mbit 512 512 mbit 5 number of i/os 40 4 80 8 16 16 6 product variant 0 .. 9 ? 7 die revision a first b second cthird d fourth 8 package, lead-free status c fbga, lead containing e tsop, lead- and halogen-free f fbga, lead- and halogen-free t tsop, lead containing 9 power ? standard power product 10 speed grade ?4 ddr500b ?4a ddr500a ?5 ddr400b ?5a ddr400a ?6 ddr333b
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 41 03292006-u5an-6ti1 list of illustrations figure 1 configuration for x4 organization, tfbga-60, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2 configuration for x8 organization, tfbga-60, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 configuration for x16 organization, tfbga-60, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 pin configuration tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5 ac output load circuit diagram / timing reference load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6 package outline p(g)-tsopii-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 7 package outline p-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 8 package outline p-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 42 03292006-u5an-6ti1 list of tables table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 ordering information for rohs compliant products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 ordering information for lead-containing products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5 abbreviations for ball type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10 mode register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13 truth table 1: commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14 truth table 2: dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 15 truth table 3: clock enable (cke). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 16 truth table 4: current state bank n - command to bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17 truth table 5: current state bank n - command to bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18 truth table 6: concurrent auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 20 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21 electrical characteristics and dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 22 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23 ac timing - absolute specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 24 ac timing - absolute specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 25 i dd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 26 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 27 example for nomenclature fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 28 ddr memory components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
hyb25d128[40/80/16]0c[c/e/f/t] 128-mbit double-data-rate sdram internet data sheet rev. 1.70, 2008-04 43 03292006-u5an-6ti1 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 configuration for tfbga-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 configuration for tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 burst type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4truthtables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 product nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
edition 2008-04 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sh eet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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